<![CDATA[Zero to ASIC Course]]>https://www.podcasts.com/zero-to-asic-course<![CDATA[Zero to ASIC Course]]>https://www.podcasts.com/zero-to-asic-coursehttps://s3.amazonaws.com/podcasts-image-uploads/zero-to-asic-course-1400x1400.pngmatt@zerotoasiccourse.comNoNoenMatt Venn 2025<![CDATA[Surviving Space: Radiation, Bit Flips, and Naked Silicon. An interview with Matthew Gill]]>A deep dive into radiation, bit flips, orbital hot spots, and what it really takes for silicon to survive in low Earth orbit.

Follow Matthew Gill: https://www.linkedin.com/in/42-matthew-gill/

00:00 Intro 
01:30 Matthew is a nuclear engineer 
02:26 How do you test without going to orbit? 
07:01 How does a bit flip happen? 
09:00 What does a hardened PDK and tooling look like? 
11:31 ESD testing 
14:15 RP2040 on HUNITY 
19:39 What is LEO like? 
23:35 Building a sensor to measure these effects 
25:22 Open source silicon intersecting with space 
30:26 What kind of shielding could we add? 
33:54 Van Allen belts 
39:18 Error detection 
41:28 Wafer variability 
44:05 Managing thermals 
49:44 Thanks
]]>A deep dive into radiation, bit flips, orbital hot spots, and what it really takes for silicon to survive in low Earth orbit.

Follow Matthew Gill: https://www.linkedin.com/in/42-matthew-gill/

00:00 Intro 
01:30 Matthew is a nuclear engineer 
02:26 How do you test without going to orbit? 
07:01 How does a bit flip happen? 
09:00 What does a hardened PDK and tooling look like? 
11:31 ESD testing 
14:15 RP2040 on HUNITY 
19:39 What is LEO like? 
23:35 Building a sensor to measure these effects 
25:22 Open source silicon intersecting with space 
30:26 What kind of shielding could we add? 
33:54 Van Allen belts 
39:18 Error detection 
41:28 Wafer variability 
44:05 Managing thermals 
49:44 Thanks
]]>https://www.podcasts.com/zero-to-asic-course/episode/surviving-space-radiation-bit-flips-and-naked-silicon-an-interview-with-matthew-gillMon, 19 Jan 2026 15:08:58 +0000Matt VennMatt VennFull3007917489321c2-e973-44a4-98e3-009d3543b962<![CDATA[Get started with Analog - Interview with Nanik Adnani.]]>take my analog course: https://www.zerotoasiccourse.com/analog/
Nanik's distortion ASIC: https://www.tinytapeout.com/chips/tt0...
Kelly Heaton's analog birds: https://www.kellyheatonstudio.com/dee...

--

00:00 Intro 
00:55 Nanik Adnani 
01:52 Why analog 
03:46 Horizontal vs Vertical IP block s
09:20 Advice for getting into industry 
11:20 Analog Birds by Kelly Heaton 
15:30 Guitar Distortion Pedal on Tiny Tapeout 
17:50 The schematic isn't the hard part 
20:51 130nm isn't as far from 7nm as you think 
23:07 Do a Tiny Tapeout!
]]>take my analog course: https://www.zerotoasiccourse.com/analog/
Nanik's distortion ASIC: https://www.tinytapeout.com/chips/tt0...
Kelly Heaton's analog birds: https://www.kellyheatonstudio.com/dee...

--

00:00 Intro 
00:55 Nanik Adnani 
01:52 Why analog 
03:46 Horizontal vs Vertical IP block s
09:20 Advice for getting into industry 
11:20 Analog Birds by Kelly Heaton 
15:30 Guitar Distortion Pedal on Tiny Tapeout 
17:50 The schematic isn't the hard part 
20:51 130nm isn't as far from 7nm as you think 
23:07 Do a Tiny Tapeout!
]]>https://www.podcasts.com/zero-to-asic-course/episode/get-started-with-analog-interview-with-nanik-adnaniTue, 04 Nov 2025 14:57:14 +0000Matt VennMatt VennFull00:24:41ccc0006e-e503-46db-9df2-0b5996e84c73<![CDATA[Testing your ASIC in Space! An interview with Tibor Herman and Pat Deegan]]>Tibor's slides: https://docs.google.com/presentation/...
Tiny Tapeout 6: https://tinytapeout.com/runs/tt06/
Test code repository: https://github.com/psychogenic/spasic...
Chat on the discord: https://tinytapeout.com/discord
Sign up for the newsletter: https://tinytapeout.com/#sign-up

00:00 Intro 
00:21 Tibor Bio 
02:31 HUNITY 
05:41 Previous missions 
10:34 What orbit will it fly in? 
17:09 Solar Panel Deployment 
19:21 Mission Goals 
24:07 Inside HUNITY 
34:42 Tiny Tapeout integration 
41:58 How to get involved 
43:17 Communications 
44:34 Sponsors 
46:19 Vibration tests 
48:30 Picking up the signals
]]>Tibor's slides: https://docs.google.com/presentation/...
Tiny Tapeout 6: https://tinytapeout.com/runs/tt06/
Test code repository: https://github.com/psychogenic/spasic...
Chat on the discord: https://tinytapeout.com/discord
Sign up for the newsletter: https://tinytapeout.com/#sign-up

00:00 Intro 
00:21 Tibor Bio 
02:31 HUNITY 
05:41 Previous missions 
10:34 What orbit will it fly in? 
17:09 Solar Panel Deployment 
19:21 Mission Goals 
24:07 Inside HUNITY 
34:42 Tiny Tapeout integration 
41:58 How to get involved 
43:17 Communications 
44:34 Sponsors 
46:19 Vibration tests 
48:30 Picking up the signals
]]>https://www.podcasts.com/zero-to-asic-course/episode/testing-your-asic-in-space-an-interview-with-tibor-herman-and-pat-deeganTue, 04 Nov 2025 14:56:03 +0000Matt VennMatt VennFull00:50:30ab8ccd29-9ca5-45a0-9745-f34b058d8fb3<![CDATA[MOSbius - A field programmable transistor array for chip designers - interview with Peter Kinget]]>Zero to ASIC course - https://www.zerotoasiccourse.com/

MOSbius - https://mosbius.org/
SSCS Chipathon - https://sscs.ieee.org/technical-commi...

00:00 Intro 
00:42 Peter Kinget 
09:59 Blinky Demo 
22:27 MOSBius Mission 
25:37 Questions - Design 
33:02 Questions - Safety 
41:37 Questions - Future plans 
50:03 Delta Sigma Demo 
57:59 Outro
]]>Zero to ASIC course - https://www.zerotoasiccourse.com/

MOSbius - https://mosbius.org/
SSCS Chipathon - https://sscs.ieee.org/technical-commi...

00:00 Intro 
00:42 Peter Kinget 
09:59 Blinky Demo 
22:27 MOSBius Mission 
25:37 Questions - Design 
33:02 Questions - Safety 
41:37 Questions - Future plans 
50:03 Delta Sigma Demo 
57:59 Outro
]]>https://www.podcasts.com/zero-to-asic-course/episode/mosbius-a-field-programmable-transistor-array-for-chip-designers-interview-with-peter-kingetTue, 04 Nov 2025 14:54:01 +0000Matt VennMatt VennFull00:59:2984659c44-db4d-4d93-85e3-b80cfd75b7d6<![CDATA[180 GHz chip design with open source tools - an interview with Shafin Hossain.]]>Design repo: https://github.com/shafinhossain/TO_M...
OpenEMS script: https://github.com/VolkerMuehlhaus/op...

00:00 Intro 
00:41 Shafin intro 
02:33 Ironman Inspiration 
04:11 G band power amplifier on IHP 130 BiCMOS 
15:37 Design Questions 
25:47 Simulation Questions 
29:00 Testing 
31:48 General Questions 
34:13 Tools Questions 
37:36 How to contact Shafin 
38:46 Plans for the future 
40:38 Outro
]]>Design repo: https://github.com/shafinhossain/TO_M...
OpenEMS script: https://github.com/VolkerMuehlhaus/op...

00:00 Intro 
00:41 Shafin intro 
02:33 Ironman Inspiration 
04:11 G band power amplifier on IHP 130 BiCMOS 
15:37 Design Questions 
25:47 Simulation Questions 
29:00 Testing 
31:48 General Questions 
34:13 Tools Questions 
37:36 How to contact Shafin 
38:46 Plans for the future 
40:38 Outro
]]>https://www.podcasts.com/zero-to-asic-course/episode/180-ghz-chip-design-with-open-source-tools-an-interview-with-shafin-hossainTue, 04 Nov 2025 14:51:46 +0000Matt VennMatt VennFull00:42:2537081d53-0d9c-4893-8fab-c701d71feb39<![CDATA[Rest in peace Z80, long live the open source Z80!]]>00:00 intro 00:56 z80 04:54 Submitted to TT07 06:52 NMOS 08:22 dynamic memory 10:28 z80 was everything in one chip 12:00 hand layout 14:10 most widely used CPU in the 80s 17:27 Tiny Tapeout compromise 18:56 voltage compatibility 19:58 Fits in 4 TT tiles 21:09 comparison table 22:47 What is Tiny Tapeout 24:28 next steps 26:29 bond pads 28:09 multicore z80 28:59 pricing 29:30 why not use an FPGA? 30:30 what to use for 1.8v core? 31:02 all the classics? 31:53 important to preserve the old chips 32:50 the plan 
35:19 how can you help?
]]>00:00 intro 00:56 z80 04:54 Submitted to TT07 06:52 NMOS 08:22 dynamic memory 10:28 z80 was everything in one chip 12:00 hand layout 14:10 most widely used CPU in the 80s 17:27 Tiny Tapeout compromise 18:56 voltage compatibility 19:58 Fits in 4 TT tiles 21:09 comparison table 22:47 What is Tiny Tapeout 24:28 next steps 26:29 bond pads 28:09 multicore z80 28:59 pricing 29:30 why not use an FPGA? 30:30 what to use for 1.8v core? 31:02 all the classics? 31:53 important to preserve the old chips 32:50 the plan 
35:19 how can you help?
]]>https://www.podcasts.com/zero-to-asic-course/episode/rest-in-peace-z80-long-live-the-open-source-z80Mon, 13 May 2024 11:19:21 +0000Matt VennMatt VennFull00:37:386c4b0356-aa31-48b1-98b7-ede5b6b7bfdc<![CDATA[Analog Philosophy - interview with Nordic’s principal IC scientist Carsten Wulff]]>* Carsten’s background and interest in analog circuit design * Open-source silicon and its benefits vs. challenges * Analog design tools evolution * Obstacles that hinder wider adoption of open-source silicon tools * Advice on approaching an analog design journey]]>* Carsten’s background and interest in analog circuit design * Open-source silicon and its benefits vs. challenges * Analog design tools evolution * Obstacles that hinder wider adoption of open-source silicon tools * Advice on approaching an analog design journey]]>https://www.podcasts.com/zero-to-asic-course/episode/analog-philosophy-interview-with-nordics-principal-ic-scientist-carsten-wulffFri, 01 Mar 2024 22:06:44 +0000Matt VennMatt VennFull00:30:4686c86ab7-7b88-42ed-a0a2-60714b9c86dc<![CDATA[Chips in days with Minimal Fab - An interview with Leo Moser]]>Talking about the minimal fab with Leo Moser. Leo recently won a competition run by minimal fab and had a design fabricated.
He's published a few blog posts about it here:

About the Minimal Fab: https://mole99.uber.space/2023/Minimal_Fab/About%20Minimal%20Fab%20and%20the%20ICPS%20PDK.html 
NAND tutorial: https://mole99.uber.space/2024/NAND_tutorial/Design%20of%20a%20NAND%20gate%20using%20the%20ICPS%20PDK.html

]]>Talking about the minimal fab with Leo Moser. Leo recently won a competition run by minimal fab and had a design fabricated.
He's published a few blog posts about it here:

About the Minimal Fab: https://mole99.uber.space/2023/Minimal_Fab/About%20Minimal%20Fab%20and%20the%20ICPS%20PDK.html 
NAND tutorial: https://mole99.uber.space/2024/NAND_tutorial/Design%20of%20a%20NAND%20gate%20using%20the%20ICPS%20PDK.html

]]>https://www.podcasts.com/zero-to-asic-course/episode/chips-in-days-with-minimal-fab-an-interview-with-leo-moserWed, 14 Feb 2024 09:30:04 +0000Matt VennMatt VennFull00:24:250d384d53-36e4-4ab2-81d9-f96f64f98686<![CDATA[An interview with Ed Conway - Silicon Supply Chains]]>Follow Ed here: https://twitter.com/EdConwaySky 
Sign up to my newsletter here: https://www.zerotoasiccourse.com/news...
]]>Follow Ed here: https://twitter.com/EdConwaySky 
Sign up to my newsletter here: https://www.zerotoasiccourse.com/news...
]]>https://www.podcasts.com/zero-to-asic-course/episode/an-interview-with-ed-conway-silicon-supply-chainsWed, 24 Jan 2024 14:01:32 +0000Matt VennMatt VennFull00:34:458b735381-157c-41da-ac76-c52edc8255e2<![CDATA[September open source silicon news update - Tiny Tapeout, Conferences, Silicon bringup & more!]]>00:00 Intro 00:10 TT boards 00:51 TT04 closes on Friday 8th 01:09 ORConf https://orconf.org/ 01:21 Wuthering Bytes 01:53 FSiC videos released https://peertube.f-si.org/video-chann... 02:04 Hackaday Supercon 2023 02:19 YUG2 https://www.linkedin.com/posts/yosysh... 02:36 Silicon news - MPW3 and 2206 03:37 IHP workshop videos    • Introduction FMD-QNC project status a...   04:04 IHP cleanroom video footage]]>00:00 Intro 00:10 TT boards 00:51 TT04 closes on Friday 8th 01:09 ORConf https://orconf.org/ 01:21 Wuthering Bytes 01:53 FSiC videos released https://peertube.f-si.org/video-chann... 02:04 Hackaday Supercon 2023 02:19 YUG2 https://www.linkedin.com/posts/yosysh... 02:36 Silicon news - MPW3 and 2206 03:37 IHP workshop videos    • Introduction FMD-QNC project status a...   04:04 IHP cleanroom video footage]]>https://www.podcasts.com/zero-to-asic-course/episode/september-open-source-silicon-news-update-tiny-tapeout-conferences-silicon-bringup-moreTue, 05 Sep 2023 12:39:29 +0000Matt VennMatt VennFull00:04:335d8b87e6-a14f-4a63-a539-15581a2ba6dd<![CDATA[Interviews from the Free Silicon Conference, Paris, 2023]]>Interviews with:

Luca Alloatti 
Thomas Benz 
Jørgen Kragh Jakobsen 
Thomas Parry 
Rene Scholz 
Dan Fritchman 
Harald Pretl
]]>Interviews with:

Luca Alloatti 
Thomas Benz 
Jørgen Kragh Jakobsen 
Thomas Parry 
Rene Scholz 
Dan Fritchman 
Harald Pretl
]]>https://www.podcasts.com/zero-to-asic-course/episode/interviews-from-the-free-silicon-conference-paris-2023Wed, 19 Jul 2023 12:00:12 +0000Matt VennMatt VennFull00:21:3693cf60d1-f516-420c-8f86-c4f4860c74b4<![CDATA[The MOnSter 6502 - how Eric Schlaepfer built a 6502 processor out of discrete transistors]]>Website: https://monster6502.com/ & visual 6502 http://www.visual6502.org/JSSim/index.html
Eric's socials: https://twitter.com/TubeTimeUS & https://mastodon.social/@tubetime
Other interviews: https://theamphour.com/609-open-circuits-with-eric-schlaepfer-and-windell-oskay/ & https://unnamedre.com/episode/58
]]>Website: https://monster6502.com/ & visual 6502 http://www.visual6502.org/JSSim/index.html
Eric's socials: https://twitter.com/TubeTimeUS & https://mastodon.social/@tubetime
Other interviews: https://theamphour.com/609-open-circuits-with-eric-schlaepfer-and-windell-oskay/ & https://unnamedre.com/episode/58
]]>https://www.podcasts.com/zero-to-asic-course/episode/the-monster-6502-how-eric-schlaepfer-built-a-6502-processor-out-of-discrete-transistorsMon, 12 Jun 2023 10:13:28 +0000Matt VennMatt VennFull00:50:34419828a6-08bd-4181-9953-8e73dfecf726<![CDATA[First chip designed with ChatGPT? An interview with Dr. Hammond Pearce & Jason Blocklove]]>https://arxiv.org/abs/2305.13243
00:00 Intro 01:21 Hardware security 02:54 How long have they been using AI to generate Verilog 05:26 Methodology 17:40 Humans in the loop 21:21 Some designs already taped out on TinyTapeout 3 26:49 How to contact
]]>https://arxiv.org/abs/2305.13243
00:00 Intro 01:21 Hardware security 02:54 How long have they been using AI to generate Verilog 05:26 Methodology 17:40 Humans in the loop 21:21 Some designs already taped out on TinyTapeout 3 26:49 How to contact
]]>https://www.podcasts.com/zero-to-asic-course/episode/first-chip-designed-with-chatgpt-an-interview-with-dr-hammond-pearce-jason-blockloveMon, 12 Jun 2023 10:12:19 +0000Matt VennMatt VennFull00:27:3396539c1a-6e8b-4b6f-a7fc-a24423f6b45d<![CDATA[Analog ASIC design with digital standard cells!]]>
For TinyTapeout 3, Harald Pretl made an analog temperature sensor out of digital standard cells. In this interview he explains how he did it.
]]>
For TinyTapeout 3, Harald Pretl made an analog temperature sensor out of digital standard cells. In this interview he explains how he did it.
]]>https://www.podcasts.com/zero-to-asic-course/episode/analog-asic-design-with-digital-standard-cellsMon, 15 May 2023 10:49:49 +0000Matt VennMatt VennFull15808218a8714b8-f87b-47b6-9fb2-83fda2191b42<![CDATA[Jeremy Birch on Tiny Tapeout's static timing analysis]]>https://www.podcasts.com/zero-to-asic-course/episode/jeremy-birch-on-tiny-tapeouts-static-timing-analysisMon, 15 May 2023 10:47:07 +0000Matt VennMatt VennFull2422101828b568e-26c6-47b4-b665-3394207c7f6e<![CDATA[using X-rays to make 3D images of chips with Tomas Aidukas]]>using X-rays to make 3D images of chips with Tomas Aidukas]]>using X-rays to make 3D images of chips with Tomas Aidukas]]>https://www.podcasts.com/zero-to-asic-course/episode/using-x-rays-to-make-3d-images-of-chips-with-tomas-aidukasThu, 19 Jan 2023 15:49:15 +0000Matt VennMatt VennFull00:26:5199709829-bafa-4285-adab-23581c76d5b0<![CDATA[Jorge Marín - DC / DC converter design and the IEEE chipathon]]>Jorge Marín - DC / DC converter design and the IEEE chipathon]]>Jorge Marín - DC / DC converter design and the IEEE chipathon]]>https://www.podcasts.com/zero-to-asic-course/episode/jorge-marin-dc-dc-converter-design-and-the-ieee-chipathonThu, 19 Jan 2023 15:48:27 +0000Matt VennMatt VennFull00:36:049f2f28e7-8d77-437c-9753-83e91149f78e<![CDATA[A look back at 2022 and what I'm looking forward to in 2023]]>https://www.podcasts.com/zero-to-asic-course/episode/a-look-back-at-2022-and-what-im-looking-forward-to-in-2023Thu, 19 Jan 2023 15:43:30 +0000Matt VennMatt VennFull00:15:412263c1cf-d246-4695-a92c-958adba7a7c6<![CDATA[September news update: MPW7 & 2, GDS renders, new videos & more!]]>MPW7: https://zerotoasiccourse.com/post/mpw7_submitted/ MPW2: https://groups.google.com/g/skywater-pdk-announce/c/HelusBBUZ20 Efabless Job: https://www.linkedin.com/jobs/view/3293645910/?refId=BA5W4wSSRYOP%2FlHyVfboBw%3D%3D Correo Libre: https://www.fossi-foundation.org/2022/09/13/ecl54 Interactive GDS viewer: https://mattvenn.github.io/wokwi-verilog-gds-test/viewer/tinytapeout.html Olof's blog: https://www.linkedin.com/posts/olofkindgren_its-time-to-to-thank-uvm-and-say-goodbye-activity-6981904420531777536-iJr4?utm_source=share&utm_medium=member_desktop]]>MPW7: https://zerotoasiccourse.com/post/mpw7_submitted/ MPW2: https://groups.google.com/g/skywater-pdk-announce/c/HelusBBUZ20 Efabless Job: https://www.linkedin.com/jobs/view/3293645910/?refId=BA5W4wSSRYOP%2FlHyVfboBw%3D%3D Correo Libre: https://www.fossi-foundation.org/2022/09/13/ecl54 Interactive GDS viewer: https://mattvenn.github.io/wokwi-verilog-gds-test/viewer/tinytapeout.html Olof's blog: https://www.linkedin.com/posts/olofkindgren_its-time-to-to-thank-uvm-and-say-goodbye-activity-6981904420531777536-iJr4?utm_source=share&utm_medium=member_desktop]]>https://www.podcasts.com/zero-to-asic-course/episode/september-news-update-mpw7-2-gds-renders-new-videos-moreFri, 07 Oct 2022 08:28:08 +0000Matt VennMatt VennFull00:04:306059683e-d91c-4261-9b6b-e22a92bd51ac<![CDATA[July news & Free Silicon Conference 2022 (FSiC22)]]>https://wiki.f-si.org/index.php/FSiC2022 00:00 Intro 01:04 Charles Papon 05:18 Tristan Gingold 09:10 Staf Verhaegen 11:30 Naohiko Shimizu 16:38 Tim Edwards 20:46 Harald Pretl 21:40 Mirjana Videnovic-Misic]]>https://wiki.f-si.org/index.php/FSiC2022 00:00 Intro 01:04 Charles Papon 05:18 Tristan Gingold 09:10 Staf Verhaegen 11:30 Naohiko Shimizu 16:38 Tim Edwards 20:46 Harald Pretl 21:40 Mirjana Videnovic-Misic]]>https://www.podcasts.com/zero-to-asic-course/episode/july-news-free-silicon-conference-2022-fsic22Fri, 07 Oct 2022 08:28:01 +0000Matt VennMatt VennFull00:26:29734edc1e-2b59-46d0-996c-a3e1167292f4<![CDATA[Crafting open source standard cell libraries with James Stine]]>00:00 Intro 03:05 Teo's work on optimising adders 04:35 Proppy's work with Jupyter notebooks 05:32 Open source is the key to innovation 07:51 GF180 08:10 When teaching the design of standard cell libraries, what do students struggle most with? 10:15 What does he think engineers least understand, but should, about standard cells? 12:14 What is your tool flow? 16:00 How many cells do you need in a library? 19:24 Why do we need another cell library for GF180? 20:40 How far are we in terms of opensource tools from commercial tools? 22:20 Liberate 25:20 Does he think automated layout of standard cells will be competitive with hand layout in nanometer processes? 29:21 Are there any circuit families from the past that deserve new attention with Moore's Law slowing down? 33:10 Any theories on why nVidia would make a 7.5T standard cell library? Contact James here: james.stine@okstate.edu or on twitter: https://twitter.com/JamesStineJr]]>00:00 Intro 03:05 Teo's work on optimising adders 04:35 Proppy's work with Jupyter notebooks 05:32 Open source is the key to innovation 07:51 GF180 08:10 When teaching the design of standard cell libraries, what do students struggle most with? 10:15 What does he think engineers least understand, but should, about standard cells? 12:14 What is your tool flow? 16:00 How many cells do you need in a library? 19:24 Why do we need another cell library for GF180? 20:40 How far are we in terms of opensource tools from commercial tools? 22:20 Liberate 25:20 Does he think automated layout of standard cells will be competitive with hand layout in nanometer processes? 29:21 Are there any circuit families from the past that deserve new attention with Moore's Law slowing down? 33:10 Any theories on why nVidia would make a 7.5T standard cell library? Contact James here: james.stine@okstate.edu or on twitter: https://twitter.com/JamesStineJr]]>https://www.podcasts.com/zero-to-asic-course/episode/crafting-open-source-standard-cell-libraries-with-james-stineFri, 07 Oct 2022 08:26:44 +0000Matt VennMatt VennFull00:35:2825538a01-1c2f-4918-8262-6ca4943d69c5<![CDATA[May news update - MPW6, fast adders, Google's new portal, Free silicon conference, FIB edit]]>Teo's adders: https://github.com/mattvenn/instrumented_adder MPW6 walkthrough: https://youtu.be/MNuoYz_MM-c https://developers.google.com/silicon Free silicon conference: https://wiki.f-si.org/index.php/FSiC2022 Newsletter: https://www.zerotoasiccourse.com/newsletter/]]>Teo's adders: https://github.com/mattvenn/instrumented_adder MPW6 walkthrough: https://youtu.be/MNuoYz_MM-c https://developers.google.com/silicon Free silicon conference: https://wiki.f-si.org/index.php/FSiC2022 Newsletter: https://www.zerotoasiccourse.com/newsletter/]]>https://www.podcasts.com/zero-to-asic-course/episode/may-news-update-mpw6-fast-adders-googles-new-portal-free-silicon-conference-fib-editFri, 07 Oct 2022 08:23:18 +0000Matt VennMatt VennFull00:04:1676f2c331-f944-4744-8331-7845148bde20<![CDATA[April news update - sky130 on Google colab, optimising adders, $100 tapeout, events and MPW2 wafers]]>00:00 intro 00:13 moving pictures 00:29 Proppy put sky130 into google colab notebooks: https://colab.research.google.com/gist/proppy/964fa4b9277c3baf9e731872bbad93e4/zerotoasic_project1_1.ipynb#scrollTo=TGgki8I-wPWa 01:12 Teo's work on optimising adders https://blog.yosyshq.com/p/optimising-adders/ 01:53 MPW6 reminder 02:20 Level up your RTL call https://twitter.com/matthewvenn/status/1514927352010186754 02:46 $100 tapeout 04:26 Chips Alliance event https://chipsspring2022.sched.com/ 04:42 WOSET https://twitter.com/mguthaus/status/1521906129126666243 04:57 ChipFlow's first video: https://www.youtube.com/watch?v=rVsOZE80c-k&t=1s 05:28 Ex-ex-ex-clusive MPW2 news 05:45 Maximo's great photo of MPW1 dies: https://twitter.com/maxiborga/status/1522372084671913985]]>00:00 intro 00:13 moving pictures 00:29 Proppy put sky130 into google colab notebooks: https://colab.research.google.com/gist/proppy/964fa4b9277c3baf9e731872bbad93e4/zerotoasic_project1_1.ipynb#scrollTo=TGgki8I-wPWa 01:12 Teo's work on optimising adders https://blog.yosyshq.com/p/optimising-adders/ 01:53 MPW6 reminder 02:20 Level up your RTL call https://twitter.com/matthewvenn/status/1514927352010186754 02:46 $100 tapeout 04:26 Chips Alliance event https://chipsspring2022.sched.com/ 04:42 WOSET https://twitter.com/mguthaus/status/1521906129126666243 04:57 ChipFlow's first video: https://www.youtube.com/watch?v=rVsOZE80c-k&t=1s 05:28 Ex-ex-ex-clusive MPW2 news 05:45 Maximo's great photo of MPW1 dies: https://twitter.com/maxiborga/status/1522372084671913985]]>https://www.podcasts.com/zero-to-asic-course/episode/april-news-update-sky130-on-google-colab-optimising-adders-100-tapeout-events-and-mpw2-wafersFri, 07 Oct 2022 08:22:21 +0000Matt VennMatt VennFull00:06:195dd76d0b-358c-4c00-9cbc-defdebcf5f6c<![CDATA[Interview with Dinesh A - Riscduino]]>
00:00 Intro
00:45 about Dinesh
02:39 Aim of Riscduino
04:50 Aim to be pin compatible and with support of compiler and libraries
06:10 Join the project - Dinesh is looking for help with analog, verification & embedded
07:30 State of the Analog IP
08:30 Tell us about your applications to MPW2, 3, 4 & 5
13:40 Great docs!
14:02 Verification
16:00 Timing analysis
19:40 What do you think about OpenLane?
24:10 Pin positions
25:40 Clock domains

]]>
00:00 Intro
00:45 about Dinesh
02:39 Aim of Riscduino
04:50 Aim to be pin compatible and with support of compiler and libraries
06:10 Join the project - Dinesh is looking for help with analog, verification & embedded
07:30 State of the Analog IP
08:30 Tell us about your applications to MPW2, 3, 4 & 5
13:40 Great docs!
14:02 Verification
16:00 Timing analysis
19:40 What do you think about OpenLane?
24:10 Pin positions
25:40 Clock domains

]]>https://www.podcasts.com/zero-to-asic-course/episode/interview-with-dinesh-a-riscduinoFri, 01 Apr 2022 09:12:35 +0000Matt VennMatt VennFull00:27:32b6d95212-082e-498f-8d36-a9019e04dace<![CDATA[February news update!]]>https://www.podcasts.com/zero-to-asic-course/episode/february-news-updateFri, 01 Apr 2022 09:11:31 +0000Matt VennMatt VennFull00:04:47b633b415-d5dd-44f6-ad00-af9106e76ed7<![CDATA[January news update]]>MPW1 silicon & bringup, MPW4 submitted, MPW5 tapeout
]]>MPW1 silicon & bringup, MPW4 submitted, MPW5 tapeout
]]>https://www.podcasts.com/zero-to-asic-course/episode/january-news-updateFri, 01 Apr 2022 09:10:27 +0000Matt VennMatt VennFull00:02:4772f33fcc-1631-4618-bc1c-1b1c9b6f0d0d<![CDATA[December news update]]>Carlos' twitter space: https://twitter.com/carlosedp/status/1469355189891125255 Silicon compiler: https://www.siliconcompiler.com/ Amaranth: https://github.com/amaranth-lang/amaranth MPW2 rerun: https://efabless.com/projects/585 MPW4 application: https://efabless.com/projects/596 Caravel restructure: https://github.com/efabless/caravel SkullFET: https://twitter.com/UriShaked/status/1472258972505812992 Will's FPGA advent calendar: https://twitter.com/WillFlux/status/1465268154733637633]]>Carlos' twitter space: https://twitter.com/carlosedp/status/1469355189891125255 Silicon compiler: https://www.siliconcompiler.com/ Amaranth: https://github.com/amaranth-lang/amaranth MPW2 rerun: https://efabless.com/projects/585 MPW4 application: https://efabless.com/projects/596 Caravel restructure: https://github.com/efabless/caravel SkullFET: https://twitter.com/UriShaked/status/1472258972505812992 Will's FPGA advent calendar: https://twitter.com/WillFlux/status/1465268154733637633]]>https://www.podcasts.com/zero-to-asic-course/episode/december-news-updateWed, 22 Dec 2021 13:18:45 +0000Matt VennMatt VennFull00:03:52december-news-update<![CDATA[Interview with Myrtle Shah: MPW3 with Coriolis, Amaranth, Flexcell & PDKMaster]]>MPW3 App: SoC https://efabless.com/projects/481 SoC source: https://github.com/ChipFlow/caravel_user_project_mpw3.git Amaranth: https://github.com/amaranth-lang/amaranth
]]>MPW3 App: SoC https://efabless.com/projects/481 SoC source: https://github.com/ChipFlow/caravel_user_project_mpw3.git Amaranth: https://github.com/amaranth-lang/amaranth
]]>https://www.podcasts.com/zero-to-asic-course/episode/interview-with-myrtle-shah-mpw3-with-coriolis-amaranth-flexcell-pdkmasterWed, 22 Dec 2021 11:57:08 +0000Matt VennMatt VennFull00:20:28interview-with-myrtle-shah-mpw3-with-coriolis-amaranth-flexcell-pdkmaster<![CDATA[Interview with Staf from Chips4Makers]]>In this interview we talk about Staf's recent tapeout, the flexcell standard cell generator and pdk master - a kind of API for pdks.
Staf also gives his opinions on the state of the industry and whether we at an inflection point for open source silicon.
]]>In this interview we talk about Staf's recent tapeout, the flexcell standard cell generator and pdk master - a kind of API for pdks.
Staf also gives his opinions on the state of the industry and whether we at an inflection point for open source silicon.
]]>https://www.podcasts.com/zero-to-asic-course/episode/interview-with-staf-from-chips4makersMon, 29 Nov 2021 13:28:09 +0000Matt VennMatt VennFull00:25:39interview-with-staf-from-chips4makers<![CDATA[November news update]]>
https://youtu.be/goOzeELjjnI

]]>
https://youtu.be/goOzeELjjnI

]]>https://www.podcasts.com/zero-to-asic-course/episode/november-news-updateThu, 25 Nov 2021 15:55:22 +0000Matt VennMatt VennFull00:04:16november-news-update<![CDATA[Matt Guthaus - OpenRAM]]>In this interview with Matt Guthaus, we talk about:

  • Recap - what is OpenRAM
  • Why do we need a memory compiler like OpenRAM?
  • 3 phases of OpenRAM development
  • What’s changed since FOSSi dialup
  • MPW2 tapeout of OpenRAM
  • Test modes
  • What was hard about MPW2
  • DRC issues
  • Status of OpenLANE support for OpenRAM
  • Future plans for OpenRAM
  • Access to resistive RAM, hopefully for MPW4
]]>In this interview with Matt Guthaus, we talk about:

  • Recap - what is OpenRAM
  • Why do we need a memory compiler like OpenRAM?
  • 3 phases of OpenRAM development
  • What’s changed since FOSSi dialup
  • MPW2 tapeout of OpenRAM
  • Test modes
  • What was hard about MPW2
  • DRC issues
  • Status of OpenLANE support for OpenRAM
  • Future plans for OpenRAM
  • Access to resistive RAM, hopefully for MPW4
]]>https://www.podcasts.com/zero-to-asic-course/episode/matt-guthaus-openramThu, 12 Aug 2021 12:47:28 +0000Matt VennMatt VennFull00:31:56matt-guthaus-openram<![CDATA[Tom Spyrou - OpenROAD development, aim, roadmap and integration with OpenLANE]]>Tom Spyrou is a long time EDA developer who has worked at large and small companies.

  • In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation.
  • He was the original architect of PrimeTime STA algorithm.
  • Manager of Cadence Common timing Engine and precursor to Open Access
  • Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

Since 2019 he has been the Chief Architect and Technical Project Manager of OpenROAD since 2019.

We have just heard the announcement that OpenLANE will become the defacto flow for OpenROAD.

So I felt very lucky that he was willing to spend half an hour talking to us about a wide range of topics including:

  • OpenROAD history & context
  • What is the aim of OpenROAD
  • State of the art in industry vs research
  • Training the next generation of EDA developers
  • Shortage of EDA developers
  • Use of other PDKs besides Sky130
  • Value of open source PDKs
  • Roadmap and improvements: PPA
  • Machine learning additions for OpenROAD
  • Cloud scale compute for OpenROAD
  • OpenLANE and OpenROAD collaboration announcement
  • Future hopes
]]>Tom Spyrou is a long time EDA developer who has worked at large and small companies.

  • In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation.
  • He was the original architect of PrimeTime STA algorithm.
  • Manager of Cadence Common timing Engine and precursor to Open Access
  • Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.

Since 2019 he has been the Chief Architect and Technical Project Manager of OpenROAD since 2019.

We have just heard the announcement that OpenLANE will become the defacto flow for OpenROAD.

So I felt very lucky that he was willing to spend half an hour talking to us about a wide range of topics including:

  • OpenROAD history & context
  • What is the aim of OpenROAD
  • State of the art in industry vs research
  • Training the next generation of EDA developers
  • Shortage of EDA developers
  • Use of other PDKs besides Sky130
  • Value of open source PDKs
  • Roadmap and improvements: PPA
  • Machine learning additions for OpenROAD
  • Cloud scale compute for OpenROAD
  • OpenLANE and OpenROAD collaboration announcement
  • Future hopes
]]>https://www.podcasts.com/zero-to-asic-course/episode/tom-spyrou-openroad-development-aim-roadmap-and-integration-with-openlaneMon, 02 Aug 2021 12:27:10 +0000Matt VennMatt VennFull00:24:42tom-spyrou-openroad-development-aim-roadmap-and-integration-with-openlane<![CDATA[Dirk Koch & Nguyen Dao - Fabulous embedded FPGAs]]>One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1.


In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them.


]]>One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1.


In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them.


]]>https://www.podcasts.com/zero-to-asic-course/episode/dirk-koch-nguyen-dao-fabulous-embedded-fpgasFri, 23 Jul 2021 13:42:17 +0000Matt VennMatt VennFull00:39:09dirk-koch-nguyen-dao-fabulous-embedded-fpgas<![CDATA[Will Green: learning FPGAs with graphics and project F]]>https://www.podcasts.com/zero-to-asic-course/episode/will-green-learning-fpgas-with-graphics-and-project-fThu, 10 Jun 2021 11:17:20 +0000Matt VennMatt VennFull01:49:40will-green-learning-fpgas-with-graphics-and-project-f<![CDATA[Dan Rodrigues - first shuttle, racing the beam & retro gaming]]>00:00 Introducing Dan Rodrigues 01:15 Dan was on the first shuttle 02:30 Converting an FPGA project to an ASIC 03:17 How long it took to prepare his submission? 05:17 What kind of config changes were required? 07:50 VDP-lite - wishbone peripheral that can generate sprites and put out on VGA: https://github.com/dan-rodrigues/caravel_vdp_lite 08:45 No framebuffer 11:20 How many flip flops were required? 12:37 A look at the GDS 14:10 Framebuffer vs racing the beam 16:28 How does the wishbone part work? How can VDP-lite be controlled? 18:10 Do you have projects planned to run on the hardware 19:06 Sam Littlewood’s PCB: https://github.com/samlittlewood/caravel_carrier 25:44 Diadatp made a PR on VGA clock demo for realtime verilator rendering 26:00 Caravel test structure 27:06 Icestation32: https://github.com/dan-rodrigues/icestation-32 28:31 Recommendations from Dan about how to learn more about retro gaming 30:12 Ultimate Gameboy talk: https://www.youtube.com/watch?v=HyzD8pNlpwI]]>00:00 Introducing Dan Rodrigues 01:15 Dan was on the first shuttle 02:30 Converting an FPGA project to an ASIC 03:17 How long it took to prepare his submission? 05:17 What kind of config changes were required? 07:50 VDP-lite - wishbone peripheral that can generate sprites and put out on VGA: https://github.com/dan-rodrigues/caravel_vdp_lite 08:45 No framebuffer 11:20 How many flip flops were required? 12:37 A look at the GDS 14:10 Framebuffer vs racing the beam 16:28 How does the wishbone part work? How can VDP-lite be controlled? 18:10 Do you have projects planned to run on the hardware 19:06 Sam Littlewood’s PCB: https://github.com/samlittlewood/caravel_carrier 25:44 Diadatp made a PR on VGA clock demo for realtime verilator rendering 26:00 Caravel test structure 27:06 Icestation32: https://github.com/dan-rodrigues/icestation-32 28:31 Recommendations from Dan about how to learn more about retro gaming 30:12 Ultimate Gameboy talk: https://www.youtube.com/watch?v=HyzD8pNlpwI]]>https://www.podcasts.com/zero-to-asic-course/episode/dan-rodrigues-first-shuttle-racing-the-beam-retro-gamingWed, 05 May 2021 08:08:21 +0000Matt VennMatt VennFull00:31:14dan-rodrigues-first-shuttle-racing-the-beam-retro-gaming<![CDATA[Thomas Parry - Amateur satellite radio, Open Source vs Industry tools, beautiful analogue layout]]>00:00 Introducing Thomas Parry 00:36 Project is an amateur satellite transceiver 01:02 Thomas wanted a challenging project 01:17 His background 01:50 Working for SystematIC Design in Delft doing analogue chip design 02:29 Design split into 2 repositories, see links below 03:50 Day to day work with Cadence and MentorGraphics industry standard tools 04:25 Pay money to reduce risk - no one to shout at 05:42 Previous interviews with Diego & Lakshmi 06:04 His design process is similar 06:57 Using Klayout for layout 07:15 Using OpenLANE for a small part of the design 08:35 Still uses Magic for extraction of circuit 08:52 Nice structure in his repository 10:24 Overview of the structure of a transceiver 12:20 Difference of the visual appearance of digital vs analogue layout 12:46 Taking a look at the GDS 13:30 Control signals 13:46 Digital section - fractional N divider for the PLL 14:29 9x9 array charge pump output 15:30 VCO - do they always look like bathroom tiles? 15:55 4 inverting amplifiers arranged in a ring 16:35 Created MOSFETs with the generator in Magic, then exported into Klayout 17:08 8x4 blocks of output drivers 17:40 Compensation filter for the PLL is off-chip 18:50 Characterise bandgap in a thermal chamber 19:30 Bandgap references replicated 3 times for different measurement options 20:15 Lovely routing! 21:08 Drawn by hand… 21:14 Ruby & Python scripting for Klayout 21:45 Efabless are working to integrate Klayout more tightly into OpenLANE 22:54 Terminology corner: Corner! 24:04 Typical Typical 25:26 How to get the RF signals in and out of Caravel padring? 26:35 WLCSP 27:20 Currently IO cells are digital 27:44 First 8 pins can be switched to analogue, but not ideal for high frequency 28:16 Power amplification 28:58 What are the next steps? Complete the TX chain 30:20 How to get started with analogue design? 32:02 Python binding for spice: https://pypi.org/project/PySpice/ 33:02 Books by Behzad Razavi are recommended. Design repo: https://github.com/yrrapt/amsat_txrx_ic Shuttle application repo: https://github.com/yrrapt/caravel_amsat_txrx_ic Connect with Thomas here: https://www.linkedin.com/in/thomas-parry-60419468/]]>00:00 Introducing Thomas Parry 00:36 Project is an amateur satellite transceiver 01:02 Thomas wanted a challenging project 01:17 His background 01:50 Working for SystematIC Design in Delft doing analogue chip design 02:29 Design split into 2 repositories, see links below 03:50 Day to day work with Cadence and MentorGraphics industry standard tools 04:25 Pay money to reduce risk - no one to shout at 05:42 Previous interviews with Diego & Lakshmi 06:04 His design process is similar 06:57 Using Klayout for layout 07:15 Using OpenLANE for a small part of the design 08:35 Still uses Magic for extraction of circuit 08:52 Nice structure in his repository 10:24 Overview of the structure of a transceiver 12:20 Difference of the visual appearance of digital vs analogue layout 12:46 Taking a look at the GDS 13:30 Control signals 13:46 Digital section - fractional N divider for the PLL 14:29 9x9 array charge pump output 15:30 VCO - do they always look like bathroom tiles? 15:55 4 inverting amplifiers arranged in a ring 16:35 Created MOSFETs with the generator in Magic, then exported into Klayout 17:08 8x4 blocks of output drivers 17:40 Compensation filter for the PLL is off-chip 18:50 Characterise bandgap in a thermal chamber 19:30 Bandgap references replicated 3 times for different measurement options 20:15 Lovely routing! 21:08 Drawn by hand… 21:14 Ruby & Python scripting for Klayout 21:45 Efabless are working to integrate Klayout more tightly into OpenLANE 22:54 Terminology corner: Corner! 24:04 Typical Typical 25:26 How to get the RF signals in and out of Caravel padring? 26:35 WLCSP 27:20 Currently IO cells are digital 27:44 First 8 pins can be switched to analogue, but not ideal for high frequency 28:16 Power amplification 28:58 What are the next steps? Complete the TX chain 30:20 How to get started with analogue design? 32:02 Python binding for spice: https://pypi.org/project/PySpice/ 33:02 Books by Behzad Razavi are recommended. Design repo: https://github.com/yrrapt/amsat_txrx_ic Shuttle application repo: https://github.com/yrrapt/caravel_amsat_txrx_ic Connect with Thomas here: https://www.linkedin.com/in/thomas-parry-60419468/]]>https://www.podcasts.com/zero-to-asic-course/episode/thomas-parry-amateur-satellite-radio-open-source-vs-industry-tools-beautiful-analogue-layoutTue, 23 Mar 2021 10:00:49 +0000Matt VennMatt VennFull00:34:16thomas-parry-amateur-satellite-radio-open-source-vs-industry-tools-beautiful-analogue-layout<![CDATA[Sylvain "tnt" Munaut - testing USB peripherals on the Google/Skywater/Efabless ASIC shuttle]]>
In this interview Sylvain talks about:
1:15? why he's excited about the shuttle
4:00? what is the design he's working on
8:00? expectation vs experience with the Open Source ASIC tools
8:57? a look at the final GDS files
14:20? differences between design for ASIC vs FPGA
16:38? tap cells
17:50? antenna rules

Sylvain's previous streams on the Skywater 130nm PDK:

https://www.youtube.com/watch?v=AT_Lc...?
https://www.youtube.com/watch?v=gRYBd...?

https://www.zerotoasic.com?

]]>
In this interview Sylvain talks about:
1:15? why he's excited about the shuttle
4:00? what is the design he's working on
8:00? expectation vs experience with the Open Source ASIC tools
8:57? a look at the final GDS files
14:20? differences between design for ASIC vs FPGA
16:38? tap cells
17:50? antenna rules

Sylvain's previous streams on the Skywater 130nm PDK:

https://www.youtube.com/watch?v=AT_Lc...?
https://www.youtube.com/watch?v=gRYBd...?

https://www.zerotoasic.com?

]]>https://www.podcasts.com/zero-to-asic-course/episode/sylvain-tnt-munaut-testing-usb-peripherals-on-the-googleskywaterefabless-asic-shuttleFri, 12 Mar 2021 11:14:07 +0000Matt VennMatt VennFull00:20:14sylvain-tnt-munaut-testing-usb-peripherals-on-the-googleskywaterefabless-asic-shuttle<![CDATA[Vladimir Milovanović - putting a spectrometer on the Google/Skywater/Efabless ASIC shuttle]]>
1:00? What made you excited about the shuttle?
2:22? The spectrometer design - radar signal processing
4:00? built in self test
4:18? in & output signals
6:00? design in Chisel
10:40? ASIC vs FPGA
11:30? showing the GDS
12:24? density of the design
13:30? contact details

https://github.com/milovanovic/spectr...?

https://www.zerotoasic.com/?

]]>
1:00? What made you excited about the shuttle?
2:22? The spectrometer design - radar signal processing
4:00? built in self test
4:18? in & output signals
6:00? design in Chisel
10:40? ASIC vs FPGA
11:30? showing the GDS
12:24? density of the design
13:30? contact details

https://github.com/milovanovic/spectr...?

https://www.zerotoasic.com/?

]]>https://www.podcasts.com/zero-to-asic-course/episode/vladimir-milovanovic-putting-a-spectrometer-on-the-googleskywaterefabless-asic-shuttleFri, 12 Mar 2021 11:10:41 +0000Matt VennMatt VennFull00:14:37vladimir-milovanovic-putting-a-spectrometer-on-the-googleskywaterefabless-asic-shuttle<![CDATA[Arya Reais-Parsi - an FPGA for the Google/Skywater/Efabless ASIC shuttle]]>In this interview Arya Reais-Parsi talks about:

00:45? FPGA design is for a course
01:50? difference between other open FPGA fabrics
02:50? FPGAs as accelerators
04:27? their FPGA structure
06:30? how did they target ASIC?
09:27? GDS view of the FPGA structure
11:40? custom cells for FPGAs
14:40? making lab notes
16:00? how does actually taping something out change the feeling of the work?
17:10? how will this shuttle program changes things going forwards?
22:40? future of ASIC with more open tooling and access
24:30? toolchain for their FPGA: yosys & nextpnr

Their group's application is here:
https://github.com/ucb-cs250/caravel_...]]>In this interview Arya Reais-Parsi talks about:

00:45? FPGA design is for a course
01:50? difference between other open FPGA fabrics
02:50? FPGAs as accelerators
04:27? their FPGA structure
06:30? how did they target ASIC?
09:27? GDS view of the FPGA structure
11:40? custom cells for FPGAs
14:40? making lab notes
16:00? how does actually taping something out change the feeling of the work?
17:10? how will this shuttle program changes things going forwards?
22:40? future of ASIC with more open tooling and access
24:30? toolchain for their FPGA: yosys & nextpnr

Their group's application is here:
https://github.com/ucb-cs250/caravel_...]]>https://www.podcasts.com/zero-to-asic-course/episode/arya-reais-parsi-an-fpga-for-the-googleskywaterefabless-asic-shuttleFri, 12 Mar 2021 11:04:38 +0000Matt VennMatt VennFull00:28:10arya-reais-parsi-an-fpga-for-the-googleskywaterefabless-asic-shuttle<![CDATA[Diego Hernando - analog circuits on the Google/Skywater/Efabless ASIC shuttle]]>
  
  

  
  
00:36? Diego's background
01:30? choice of design and the new tools
02:50? digital vs analog process
09:05? op-amp specifications
12:35? schematic in xschem
13:40? open loop testbench
14:26? spice setup
15:37? simulation results
17:44? layout in magic
23:20? opamps placed in the user project wrapper of Caravel
27:20? testing the ASIC

Diego on linked.in: https://www.linkedin.com/in/diego-joa...?
Diego's ASIC submission: https://github.com/diegohernando/cara...?
xschem: https://xschem.sourceforge.io/stefan/...?




]]>
  
  

  
  
00:36? Diego's background
01:30? choice of design and the new tools
02:50? digital vs analog process
09:05? op-amp specifications
12:35? schematic in xschem
13:40? open loop testbench
14:26? spice setup
15:37? simulation results
17:44? layout in magic
23:20? opamps placed in the user project wrapper of Caravel
27:20? testing the ASIC

Diego on linked.in: https://www.linkedin.com/in/diego-joa...?
Diego's ASIC submission: https://github.com/diegohernando/cara...?
xschem: https://xschem.sourceforge.io/stefan/...?




]]>https://www.podcasts.com/zero-to-asic-course/episode/diego-hernando-analog-circuits-on-the-googleskywaterefabless-asic-shuttleFri, 12 Mar 2021 11:02:32 +0000Matt VennMatt VennFull00:29:49diego-hernando-analog-circuits-on-the-googleskywaterefabless-asic-shuttle<![CDATA[Lakshmi S - Designing a PLL for the Google/Skywater/Efabless ASIC shuttle]]>
00:00? introduction

01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...?
02:18? Questions from Niklas - time it takes, what's frustrating, fun?
05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel.
07:20? Question from Pepijn - what would you need to change to alter the PLL?
08:44? PLL overview
10:00? Lakshmi's design: Frequency divider
12:22? Phase frequency detector
13:32? Charge pump
14:37? Voltage controlled oscillator
16:40? combined designs with Diego Hernando
17:10? putting into the Caravel wrapper, adding space
18:56? Question from Brady - why design an integrated loop filter
20:01? Questions from Top - are there schematics? Process corners and ngspice convergence
22:05? Question from Steven: post silicon testing

Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/?
Repo: https://github.com/lakshmi-sathi/avsd...]]>
00:00? introduction

01:04? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi...?
02:18? Questions from Niklas - time it takes, what's frustrating, fun?
05:40? Are the tools ready for mixed signal designs - DRC violations in Caravel.
07:20? Question from Pepijn - what would you need to change to alter the PLL?
08:44? PLL overview
10:00? Lakshmi's design: Frequency divider
12:22? Phase frequency detector
13:32? Charge pump
14:37? Voltage controlled oscillator
16:40? combined designs with Diego Hernando
17:10? putting into the Caravel wrapper, adding space
18:56? Question from Brady - why design an integrated loop filter
20:01? Questions from Top - are there schematics? Process corners and ngspice convergence
22:05? Question from Steven: post silicon testing

Lakshmi on Linked.in: https://www.linkedin.com/in/lakshmis96/?
Repo: https://github.com/lakshmi-sathi/avsd...]]>https://www.podcasts.com/zero-to-asic-course/episode/lakshmi-s-designing-a-pll-for-the-googleskywaterefabless-asic-shuttleFri, 12 Mar 2021 10:57:38 +0000Matt VennMatt VennFull00:24:31lakshmi-s-designing-a-pll-for-the-googleskywaterefabless-asic-shuttle<![CDATA[Anton Blanchard - Microwatt: a 64 bit OpenPOWER core, VHDL and OpenLANE.]]>https://www.podcasts.com/zero-to-asic-course/episode/anton-blanchard-microwatt-a-64-bit-openpower-core-vhdl-and-openlaneThu, 11 Mar 2021 17:45:58 +0000Matt VennMatt VennFull01:00:27anton-blanchard-microwatt-a-64-bit-openpower-core-vhdl-and-openlane<![CDATA[Tim Edwards - what happens between ASIC submission and sending to Skywater?]]>00:12 Tim Edwards introduction
01:00 next steps after submission before files sent to Skywater
02:00 infrastructure - getting all the latest from everyone's repositories
03:05 size of the repos can be a problem
03:41 revolutionary part of this run is that everything is Open Source down to the GDS
04:51 Open Source PDK is what makes it possible to do this for eFabless
05:12 Why didn't we submit the source rather than the final GDS?
09:42 Got all the GDS2 files from the repos, what's the next step?
10:00 3 scripts, 1st applies a user id
13:04 2nd script does fill generation
16:14 3rd script does compositing
19:39 DRC count for Caravel
23:00 lots of people have helped make this happen
23:50 biggest project at eFabless
24:00 When do you think the files will get sent to Skywater?

Open Source VLSI tools: http://opencircuitdesign.com/
eFabless: https://efabless.com/company]]>00:12 Tim Edwards introduction
01:00 next steps after submission before files sent to Skywater
02:00 infrastructure - getting all the latest from everyone's repositories
03:05 size of the repos can be a problem
03:41 revolutionary part of this run is that everything is Open Source down to the GDS
04:51 Open Source PDK is what makes it possible to do this for eFabless
05:12 Why didn't we submit the source rather than the final GDS?
09:42 Got all the GDS2 files from the repos, what's the next step?
10:00 3 scripts, 1st applies a user id
13:04 2nd script does fill generation
16:14 3rd script does compositing
19:39 DRC count for Caravel
23:00 lots of people have helped make this happen
23:50 biggest project at eFabless
24:00 When do you think the files will get sent to Skywater?

Open Source VLSI tools: http://opencircuitdesign.com/
eFabless: https://efabless.com/company]]>https://www.podcasts.com/zero-to-asic-course/episode/tim-edwards-what-happens-between-asic-submission-and-sending-to-skywaterThu, 11 Mar 2021 17:42:38 +0000Matt VennMatt VennFull00:30:13tim-edwards-what-happens-between-asic-submission-and-sending-to-skywaternoMon, 19 Jan 2026 15:08:58 +0000